The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and apparatus for address decoding of embedded DRAM (eDRAM) devices.
As a result of the package/pin limitations associated with discrete, self-contained devices such as DRAMs, memory circuit designers have used certain multiplexing techniques in order to access the large number of internal memory array addresses through the narrow, pin-bound interfaces. Because these discrete DRAMs have been in use for some time, a standard interface has understandably emerged over the years for reading and writing to these arrays.
More recently, embedded DRAM (eDRAM) macros have been offered, particularly in the area of Application Specific Integrated Circuit (ASIC) technologies. For example, markets in portable and multimedia applications such as cellular phones and personal digital assistants utilize the increased density of embedded memory for higher function and lower power consumption. Unlike their discrete counterparts, the eDRAM devices do not have the limited I/O pin interfaces with associated memory management circuitry. In fact, the typical I/O counts for eDRAM devices can number in the hundreds.
Another possible use for the newer eDRAM devices would be the ability to use them interchangeably with existing SDRAM modules, thereby forming a structure utilizing a standard SDRAM interface, but having an embedded memory module therein. Unfortunately, the memory array configurations for a standard SDRAM and an eDRAM are somewhat different. In addition, the existing multiplexing and addressing schemes used by a memory manager (e.g., a hard disk controller) are not suited for use with an eDRAM structure, particularly with regard to the addressing of the array. For example, the limited I/O pin interfaces in SDRAM memory management circuitry have resulted in the use of a “time shared” addressing method, wherein a row address is presented at an initial clock cycle and held in a register until the corresponding column address is presented at a later clock cycle. The eDRAM devices, on the other hand, do not make use of these time shared addressing techniques.